AS THE TECHNOLOGY NODE OF CMOS SHRINKS, BACKEND OF LINE (BEOL) INTERCONNECT FACES RC DELAY & RELIABILITY RISKS - ELECTRO-MIGRATION (EM), TIME DEPENDENT DIELECTRIC BREAKDOWN (TDDB) IN CU/LOW-K INTERCONNECTS. SCALING DOWN CRITICAL DIMENSION CAUSES SURGE IN RC TIME DELAY RESULTING IN DEGRADATION OF HIGH SPEED PERFORMANCE OF MICROPROCESSORS. THIS IS A CRITICAL ISSUE FOR ANY NEW GENERATION TECHNOLOGY NODE AND IN ORDER TO ENHANCE THE SPEED PERFORMANCE WIRING SHEET RESISTANCE AND CAPACITANCE NEEDS TO BE CONTROLLED.

BEOL CAPACITANCE IS PRIMARILY GOVERNED BY TWO COMPONENTS: INTER METAL DIELECTRIC (IMD) AND DIELECTRIC BARRIER FILMS. FOR CAPACITANCE REDUCTION, TYPICALLY LOWERING DIELECTRIC CONSTANT OF THE BARRIER FILM IS PREFERRED OVER LOW-K DUE TO MECHANICAL CONSIDERATIONS, INTEGRATION CHALLENGES AND RELIABILITY REQUIREMENTS. SEVERAL OTHER SINGLE, BILAYER OR TRI-LAYER DIELECTRIC BARRIER FILMS HAVE ALSO BEEN EVALUATED BY THE INDUSTRY TO WIN CAPACITANCE GAIN BY EITHER REDUCING THE DIELECTRIC CONSTANT OR THINNING THE BARRIER FILM THICKNESS.

IN THIS LECTURE, WE WILL DISCUSS THE DEVELOPMENT PROCESS AND FUTURE OF THE LOGIC BEOL PROCESS.